Low level access to RISC-V processors
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bors[bot] 0eda3c511c
Merge #32
3 years ago
.github A unified contributing experience. 4 years ago
bin add riscv32i target 3 years ago
ci Enable gcc caching 4 years ago
src ucause only as readable bits 3 years ago
.gitignore Implement asm functions 4 years ago
.travis.yml Add MSRV policy 4 years ago
CODE_OF_CONDUCT.md Rename RISCV to RISC-V 4 years ago
Cargo.toml Do not use bare-metal v0.2.5 (changes MSRV) 3 years ago
README.md Rename RISCV to RISC-V 4 years ago
asm.S Declare all the CSR registers in asm.S 4 years ago
asm.h Declare all the CSR registers in asm.S 4 years ago
assemble.sh add riscv32i target 3 years ago
build.rs Implement asm functions 4 years ago
check-blobs.sh Implement asm functions 4 years ago

README.md

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riscv

Low level access to RISC-V processors

This project is developed and maintained by the RISC-V team.

Documentation

License

Copyright 2019 RISC-V team

Permission to use, copy, modify, and/or distribute this software for any purpose with or without fee is hereby granted, provided that the above copyright notice and this permission notice appear in all copies.

THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.

Code of Conduct

Contribution to this crate is organized under the terms of the Rust Code of Conduct, the maintainer of this crate, the RISC-V team, promises to intervene to uphold that code of conduct.